1. Field of the Invention
The present invention relates to a variable delaying circuit for easily controlling a delay time.
2. Description of the Related Art
Generally, hardware of an electronic unit is composed of a plurality of integrated circuits. Most of control commands that designate the operations of such a unit are composed of electric control signals. Thus, to properly control the electric unit, a technology for precisely adjusting control signals is required. In addition, control signals have a time base fluctuation element (namely, jitter). When a jitter takes place in a control signal, the time base of the control signal should be compensated so as to remove the jitter therefrom.
Corresponding to such a technology, the variable delaying circuit should precisely control a delay amount (namely, so-called high resolution).
Next, related art references of conventional delaying circuits will be described.
FIG. 3 is a circuit diagram showing a related art reference of a variable delaying circuit.
In FIG. 3, a first terminal of a resistor 5 is connected to an input terminal 1. A first terminal of a capacitor 6 and a first input terminal of a comparator 4 are connected to a second terminal of the resistor 5. A second terminal of the capacitor 6 is connected to a second power supply 22. A second input terminal of the comparator 4 is connected to a reference input terminal 2. An output terminal of the comparator 4 is connected to an output terminal 3.
In this example, one input terminal connected to the second terminal of the resister 5 and the first terminal of the capacitor 6 are referred to as node A. The other terminal connected to the reference input terminal 2 is referred to as node B.
Next, with reference to FIGS. 4 and 5, most typical structures of the comparator 4 will be described.
FIG. 4 shows an example of the structure of the comparator 4 that is composed of only MOS transistors.
In FIG. 4, a gate of an NMOS transistor 35 is connected to an input terminal 31. A gate of an NMOS transistor 36 is connected to a reference input terminal 2. A gate of a PMOS transistor 33 and a gate of a PMOS transistor 34 are connected to a drain of the NMOS transistor 35. A drain of the PMOS transistor 34 and a gate of an NMOS transistor 38 are connected to a drain of the NMOS transistor 36. A drain of an NMOS transistor 37 is connected to sources of the NMOS transistors 35 and 36. A source of the NMOS transistor 38 and a drain of an NMOS transistor 39 are connected to an output terminal 3. Sources of the PMOS transistors 33 and 34 and a drain of the NMOS transistor 38 are connected to a first power supply 21. Sources of the NMOS transistors 37 and 39 are connected to a second power supply 22. Gates of the NMOS transistors 37 and 39 are connected to a constant voltage source 32.
FIG. 5 shows an example of the structure of the comparator 4 that is composed of only bipolar transistors and resistors.
In FIG. 5, a base of an NPN transistor 42 is connected to an input terminal 31. A base of an NPN transistor 43 is connected to a reference input terminal 2. A first terminal of a resistor 40 is connected to a collector of the NPN transistor 42. A first terminal of a resistor 41 and a base of an NPN transistor 46 are connected to a collector of the NPN transistor 43. A collector of an NPN transistor 44 is connected to emitters of the NPN transistors 42 and 43. A first terminal of a resistor 45 is connected to an emitter of the NPN transistor 44. An emitter of the NPN transistor 46 and a collector of an NPN transistor 47 are connected to an output terminal 3. A first terminal of a resistor 48 is connected to an emitter of the NPN transistor 47. Second terminals of the resisters 40 and 41 and a collector of the NPN transistor 46 are connected to a first power supply 21. Second terminals of the resistors 45 and 48 are connected to a second power supply 22. Bases of the NPN transistors 44 and 47 are connected to a constant voltage source 32.
In each of the comparators shown in FIGS. 4 and 5, the input terminal 31 is referred to as the node A. The input terminal 2 is referred to as the node B. In these examples, a logic signal is supplied to the node A. A reference voltage that allows a constant voltage to be kept is supplied to the node B. The output terminal 3 outputs the result of which the constant voltage of the node B and the voltage of the logic signal of the node A have been compared. In reality, assuming that the voltage of the node A is larger than the reference voltage of the node B, the output terminal 3 outputs a signal in the high level that is closer to the first power supply voltage. Assuming that the voltage of the node A is smaller than the reference voltage of the node B, the output terminal 3 outputs a signal in the low level that is closer to the second power supply voltage.
Next, the operation of the comparator 4 with the structure shown in FIG. 4 will be described. When the voltage of the node A (input terminal 31) is larger than the reference voltage of the node B (input terminal 2), the NMOS transistor 35 is in the connected state and the NMOS transistor 36 is in the open state. Since the PMOS transistor 34 is in the connected state, the voltage of the first power supply 21 is supplied to the gate of the NMOS transistor 38. Thus, the NMOS transistor 38 is in the connected state. The output terminal 3 outputs a signal in the high level that is closer to the first power supply voltage. When the voltage of the node A (input terminal 31) is smaller than the reference voltage of the node B (input terminal 2), the NMOS transistor 35 is in the open state and the NMOS transistor 36 is in the connected state. Since the NMOS transistors 36 and 37 are in the connected state, a voltage that is closer to the second power supply 22 is supplied to the gate of the NMOS transistor 38. Thus, the NMOS transistor 38 is in the open state. The output terminal 3 outputs a signal in the low level that is closer to the second power supply voltage.
Next, the operation of the comparator 4 with the structure shown in FIG. 5 will be described. When the voltage of the node A (input terminal 31) is larger than the reference voltage of the node B (input terminal 2), the NPN transistor 42 is in the connected state and the NPN transistor 43 is in the open state. A voltage of the first power supply 21 is supplied to the base of the NPN transistor 46 through the resistor 41. Thus, the NPN transistor 46 is in the connected state. The output terminal 3 outputs a signal in the high level that is closer to the first power supply voltage. When the voltage of the node A (input terminal 31) is smaller than the reference voltage of the node B (input terminal 2), the NPN transistor 42 is in the open state and the NPN transistor 43 is in the connected state. Since the NPN transistors 43 and 44 are in the connected state, a voltage that is closer to the voltage of the second power supply 22 is supplied to the base of the NPN transistor 46. Thus, the NPN transistor 46 is in the open state. The output terminal 3 output a signal in the low level that is closer to the voltage of the second power supply.
The conventional variable delaying circuit shown in FIG. 3 can control a delay time corresponding to the operation of the above-described comparators.
In FIG. 3, assuming that a logic signal whose signal level varies from the low level to the high level is supplied to the input terminal 1, that the amplitude of the logic signal is denoted by E, that the resistance of the resistor 5 is denoted by R, that the capacitance of the capacitor 6 is denoted by C, and that the varying time of the logic signal is denoted by t, the voltage V.sub.A of the node A is expressed by the following formula. EQU V.sub.A (t)=E-E.times.{exp(-t/C.times.R)} (1)
Formula (1) represents that the voltage of the node A depends on an exponential variation of the resistance R of the resistor 5 and the capacitance C of the capacitor 6 as a time elapses.
For easy understanding of the voltage of the node A, FIG. 6 shows a waveform in a simulation.
With reference to FIG. 6, the operation of the related art reference will be described. Assuming that a signal shown in FIG. 6 is input to the node A (input terminal 31) and that a constant voltage the is the same as the voltage of the signal shown in FIG. 6 (this voltage is denoted by V.sub.0), the comparator 4 determines whether the signal level of the signal is the high level or the low level of the signal at time (t.sub.0) shown in FIG. 6. In other words, when the varying time t is in the range from 0 to t.sub.0, the comparator 4 determines the level of the signal as the low level. In contrast, when the varying time t exceeds t.sub.0, the comparator 4 determines the level of the signal as the low level. In this condition, to obtain a delay varying time, assuming that the reference voltage of the node B (reference input terminal 2) is varied from a constant voltage that is the same as the voltage (V.sub.0) of the signal shown in FIG. 6 to a constant voltage that is the same as (V.sub.1), the comparator 4 determines whether the signal level of the signal is the high level or the low level at time t.sub.1 shown in FIG. 6. In other words, in FIG. 6, when the varying time is in the range from 0 to t.sub.1, the comparator 4 determines the signal level of the signal as the low level. When the varying time exceeds t.sub.1, the comparator 4 determines the level of the signal as the high level.
In other words, for example, in the case that the signal level varies from the low level to the high level, when a constant voltage of the node B (reference input terminal 2) varies from V.sub.0 to V.sub.1, the conventional variable delaying circuits obtain a delay varying time from t.sub.0 to t.sub.1.
However, in the above-described conventional variable delaying circuits, an exponential time variation of a logic signal that depends on a resistor and a capacitor is supplied to one input terminal of a comparator. By varying the reference voltage of the other input terminal and a determination point of the low level and the high level that the comparator determines, a delay variable time is obtained. However, in the conventional circuits, the delay varying time is not constant to the varying amount of the reference voltage. With reference to FIG. 6, this problem will be described in the following.
In FIG. 6, as was described above, elements that relate to the delay varying time are varying amounts (V.sub.0, V.sub.1, and V.sub.2) of the reference voltage supplied to the comparator. In other words, in the case that the signal level of the signal varies from the low level to the high level, when the constant voltage of the node B (reference input terminal 2) shown in FIG. 3 varies from V.sub.0 to V.sub.1, the conventional variable delaying circuits can obtain a delay varying time from t.sub.0 to t.sub.1. In FIG. 6, the varying amount of the delay time to the varying amount of the reference voltage is around 20 nsec/V. When the constant voltage of the node B (reference input terminal 2) varies from V.sub.1 to V.sub.2, the delay varying time varies from t.sub.1 to t.sub.2. In FIG. 6, the varying amount of the delay time to the varying amount of the reference voltage is around 43 nsec/V. As is clear from Formula (1), the reason why the delay varying time largely depends on the constant voltage supplied to the node B is in that the variation of the logic signal of the node A (input terminal 1) shown in FIG. 3 is always exponentially proportional to the time variation. This is because the current that flows in the capacitor 6 shown in FIG. 3 is not constant. In other words, in the conventional variable delaying circuits, the delay varying amount to the varying amount of the reference input voltage is too large. Thus, a desired delay varying time cannot be precisely controlled with the reference input voltage. Thus, a correct delay controlling amount cannot be obtained. In addition, as is clear from Formula (1), since the varying amounts of the resistance R and the capacitance C are exponentially proportional to the time variation. Thus, the delay controlling amount is largely affected by the process dependency of the resistance R and the capacitance C.